Programmable Device Circuits and Systems

M. Janaki Rani ¹, S. Malarkkan ²

Affiliations
1 Area of Low Power VLSI Design in Sathyabama University, Chennai, IN
2 Manakula Vinayagar Institute of Technology, Puducherry, IN

Abstract

As the VLSI technology and supply/threshold voltage keep on reducing, leakage power has turn out to be highly important in the power wastage of present CMOS circuits. In order to reduce the leakage current is evolving as very significant in low-power design. This provides great opportunity for the researchers to look for better technique to reduce the leakage power. Several methods thus have been provided by the researchers to decrease the leakage power consumption. Input Vector Control (IVC) method is depends on the inspection that the leakage power in a CMOS logic gate is based on the gate input state and a good input vector has a capability to decrease the leakage current when the circuit is in the sleep mode. This technique is found to be better technique for leakage power reduction. When paths in circuits happen to deeper, the input vector control techniques turn out to be unsuccessful since gates with deep levels are difficult to be affected by the input vector. One way to handle this problem is the gate replacement method. Gate replacement technique is nothing but replacing a gate with another gate with sleep mode attached in it. This paper combines IVC and gate replacement technique for better reduction in leakage current. The simulation result shows that the proposed technique resulted in better reduction in leakage current when compared to conventional techniques.

Keywords

Leakage Current, Input Vector Control (IVC), Gate Replacement, Worst Leakage State (WLS).

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B. Sathyabama ¹, S. Malarkkan ²

Affiliations
1 Area of Low Power VLSI Design in Sathyabama University, Chennai, IN
2 Manakula Vinayagar Institute of Technology, Puducherry, IN

Abstract

One of the significant factors for evaluating the circuit performance is transistor sizing. Thus for offering better evaluation, an optimal size of transistor is required. The purpose of the optimization is to reduce the power-delay product or the energy requirement by the circuit. The power and delay are mainly based on the size of transistor. There are many technique exists for optimizing the size of transistor for reducing the power consumption. But all these techniques resulted in poor performance for larger transistors. To overcome those demerits, genetic algorithm is used. Genetic algorithm has the capacity of minimizing the search problem complexity uses the transistor sizing which is usually a type of search problem in the large multidimensional search space for energy reduction. This technique shows better performance when compared to the Hybrid Tree Structure technique. For further improving the performance, a modified genetic algorithm is proposed in this paper for determining the transistor size which in turn leads to better reduction of power consumption.

Keywords

Transistor Sizing, Power Optimization, Modified Genetic Algorithm.

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